Multiplexers are logic devices that select between two or more inputs to be transferred to an output. It is desirable to have a multiplexer implemented with a symmetrical structure to minimize the skew when selecting between the various inputs. It is also desirable to minimize the delay introduced through the multiplexer. Additionally, it is often desirable to have a multiplexer with multiple number of inputs, in particular more than two inputs, and sometimes an odd number of inputs, while using a minimum number of components.
Referring to FIG. 1a, a circuit 10 illustrating a four input multiplexer is shown. The multiplexer 10 has an input 12, an input 14, an input 16, an input 18 and an output 20. The input 12 receives a signal A, the input 14 receives a signal B, the input 16 receives a signal C and the input 18 receives a signal D. The output 20 presents a signal OUT. The multiplexer 10 also comprises an input 22 and an input 24 that receive a select signal SEL0 and SEL1, respectively. The multiplexer 10 presents one of the signals A, B, C or D at the output 20 in response to the select signals SEL0 and SEL1.
The multiplexer 10, while performing the function of a four input multiplexer, actually comprises a number of two input multiplexers 26a-26n. The multiplexer 26a receives the signal A and the signal B and presents an output to a first input of the multiplexer 26n. The multiplexer 26b receives the signal C and the signal D and presents a signal to a second input of the multiplexer 26n. The multiplexer 26n then presents either the signal received at the first or the second input as the signal OUT. The signal SEL0 selects between the input A and B or the input C and D and the select signal SEL1 selects between the signals received by the multiplexer 26n at the first or second inputs. Using the circuit 10 to implement a multiplexer with more than four inputs, additional number of stages must be implemented. The additional stages create additional delay through the multiplexer 10 which may result in higher skew. Additionally, if the number of inputs is not equal to 2.sup.N, circuitry may be wasted.
Referring to FIG. 1b, a basic CML two-input multiplexer 40 is shown. A transistor Q1 receives an input A_P, a transistor Q2 receives an input A_N, a transistor Q3 receives a signal B_P and a transistor Q4 receives a signal B_N. The input A_P and A_N may be a differential input and the input B_P and B_N may be a differential input. The multiplexer 40 also comprises a resistor 42, a resistor 44, and a current source 46. The multiplexer 40 represents one of the multiplexers 26a-26n.
Referring to FIG. 2, a multiplexer 50 is shown implemented using a second conventional approach. The multiplexer 50 comprises a number of transistor pairs 52a-52n that each have a differential input (i.e., A_P and A_N; B_P and B_N; C_P and C_N; and D_P and D_N, respectively) and each have a corresponding select transistor 54a-54n. The multiplexer 50 also comprises a current source 58, a resistor 60 and a resistor 62. The select transistors 54a and 54b are connected to a second stage select transistor 56a. The select transistors 54c and 54n are connected to a second stage select transistor 56n. The second stage select transistors 56a and 56n are connected to a current source 58. At the lowest level, there is one differential pair (i.e., 56a and 56n ) controlled by a pair of select lines (i.e., SEL0_P and SEL0_N). The transistors 54a-54n are stacked on top of the transistors 56a and 56n and contain two differential pairs (i.e., 54a and 54b, and 54c and 54n, respectively) . The transistors 54a-54n are controlled by a second pair of select lines (i.e., SEL1_P and SEL1_N). The top level contains the four differential pairs (52a-52n). The multiplexing operation is performed by the two lower levels (i.e., the transistors 54a-54n and 56a-56n). The circuit 50 has the disadvantages of (i) requiring multiple levels of select lines, (ii) requiring additional levels of cascading to implement more than four inputs, (iii) introducing a delay to the multiplexer due to the cascading, and (iv) increasing the internal delay, which results in higher skew. Additionally, redundant circuitry is implemented if the number of inputs is not equal to 2.sup.N.